Optimization of through Si via Last Lithography for 3d Packaging

In this paper we optimize the back-to-front overlay of Through Silicon Via (TSV) patterning for a 5μm via last process. After TSV patterning, overlay verification poses a challenge because the reference layer is buried underneath the thinned silicon wafer. For both back-to-front alignment and verification a wafer stepper equipped with a Dual Side Alignment (DSA) system is used. The stepper has a selfmetrology capability to measure back-to-front overlay at any location on the wafer and model the acquired data using industry standard lithographic error analysis techniques to enable insight into the overlay performance. The experimental wafers are fabricated by patterning the first interconnect metallization of a TSV-last test chip designed for process characterization. The wafers are then temporary bonded to a carrier and thinned to 50μm. The final process step is chemical mechanical polish (CMP) of the silicon surface. In order to investigate the overlay performance, Stepper Self Metrology (SSM) is performed at the four corners and the center of the lithography field. Multiple lithography fields per wafer and multiple wafers are measured to obtain a statistically significant data set for overlay analysis. Overlay verification is performed by dedicated software on the lithography system utilizing the DSA alignment system. The image capture determines the offset between the TSV photoresist pattern and the reference metal pattern buried under the thinned silicon wafer. Tool Induced Shift is characterized and included in the measurement routine. The verification software provides a data summary and alignment correctable variables to optimize the via-last overlay. It was observed that non-linear effects from the incoming wafers in this study were a limiting factor in the achievable overlay performance. On good quality wafers the overlay performance is better than 750nm which meets the requirements for 5μm diameter TSV’s.